The present invention relates to a data access control system for use in a disk drive including a buffer memory for storing data read from a disk and data to be written in the disk, and having a function of performing data transfer control between the disk and a host system through the buffer memory.
In a disk drive such as a hard disk drive (HDD), when an access command (read or write command) is issued from a host system (e.g., a personal computer), the CPU moves a head to a target position on the disk to read the requested data (the data accessed by the host system) from the target position or write data at the target position. The target position is a target track having a track number (cylinder number) which is a physical address corresponding to a logical address contained in a command from the host system. Note that a physical address includes a head number and a data sector number as well as a track number.
Consider an operation associated with a read command, in particular. The requested data (read data decoded into write data) read from the disk is stored in a buffer memory which is generally constituted by a RAM (Random Access Memory). Control on this buffer memory and data transfer control between the disk and the host system are executed by a disk controller (HDC). When data is read from the disk and stored in the buffer memory by a predetermined data amount, the HDC executes data transfer from the buffer memory to the host system. The HDD executes data transfer in units of data sectors.
In this system, much time is required between the instant at which the host system issues a read command and the instant at which the requested data is actually transferred from the disk drive. For this reason, in the HDD, in particular, when the host system requests access to data which has been previously read from the disk in accordance with an access request from the host system, the HDC reads the requested data from the buffer memory and transfers it to the host system. In this method, since the drive need not read the data from the disk, the processing time required for data transfer can be shortened to allow high-speed transfer of the requested data to the host system. Such a scheme is called a cache system. In the cache system, a state in which requested data is stored in the buffer memory is called a hit (cache hit).
The cache processing executed by the HDD cache system roughly includes processing for a sequential access request from the host system, and processing for a repeat access request. A sequential access request is a read access request for consecutive addresses. A repeat access request is a read access request for the same address.
As described above, the HDC stores the data read from the disk in accordance with an access request from the host system in the buffer memory. The HDC manages the data storage state (i.e., the amount of data that can be stored) of the buffer memory. If the buffer memory has no available area, and the data read from the disk cannot be stored therein, the HDC temporarily stops the read operation of data from the disk. When an area in which data can be stored (available area) is generated in the buffer memory, the HDC restarts the data read operation.
The HDC also manages data transfer between the host system and the buffer memory. More specifically, the HDC transfers the requested data stored in the buffer memory to the host system, and stops data transfer to the host system when there is no requested data to be transferred from the buffer memory. When the requested data read from the disk is stored in the buffer memory by a predetermined amount, the HDC restarts data transfer to the host system. In general, this predetermined amount is a data amount measured in data sectors, which is the minimum unit amount for a read access request.
Buffer memory management and data transfer control performed by the HDC in the HDD will be described below with reference to the block diagram of FIG. 6 and the flow chart of FIG. 7.
When a read command (read access request) is issued from a host system 200, the CPU (not shown) of an HDD 100 checks whether the read access request is a sequential access request, a repeat access request, or a normal access request (steps S31 and S32). In this case, an HDC 1 receives the read command from the host system 200, and sets it in a command register 1B (step S30). The CPU always monitors the command register 1B and recognizes the read command from the host system 200.
Assume that the read command from the host system 200 is a normal access request (NO in step S32). The HDC 1 accesses a buffer memory 2 to check whether the requested data accessed by the read command is stored in the buffer memory 2 (step S33). If the requested data is not stored in the buffer memory 2 (miss hit), the CPU executes control to seek a head to the target track on which the requested data is recorded, thereby executing a read operation of data from the disk. At this time, the CPU outputs an instruction to store the requested data (e.g., data 3A corresponding to two data sectors) read from the disk 3 and the successive data (e.g., the data corresponding to the remaining data sectors on the same track) having addresses consecutive to those of the requested data in the buffer memory 2 (step S34). The CPU also outputs an instruction to transfer the requested data to the host system 200 every time the requested data is stored in the buffer memory 2 by a predetermined amount.
The HDC 1 stores the requested data read from the disk 3 in an area 2A of the buffer memory 2, and also stores the successive data read from the disk 3 in a remaining available area 2B. In this case, the amount of data stored in the buffer memory 2 is managed by a buffer counter 1A. When a predetermined amount of requested data is stored in the area 2A of the buffer memory 2, the HDC 1 starts transferring the data to the host system 200 (step S35). At this time, the HDC 1 stores the successive data read from the disk 3 in the buffer memory 2 up to the limit of the available storage area (arrow V1), as shown in FIG. 6. When the HDC 1 transfers all the requested data to the host system 200, the CPU ends the read command from the host system 200 (YES in step S36).
When the HDC 1 transfers all the requested data from the buffer memory 2 to the host system 200 (arrow V2), the area 2A, of the buffer memory 2, which corresponds to the requested data becomes an available area. The HDC 1 therefore stores the successive data in the available area 2B of the buffer memory 2, and determines that permission is granted to read data following the successive data from the disk 3 and store the data in the available area 2A (arrow V3).
Assume that a read command as a sequential access request is issued from the host system 200 in this state (YES in step r31). That is, this command is an access request for data having an address consecutive to that of the requested data. The requested data corresponding to this sequential access request is the data that has already been stored in the available area 2B of the buffer memory 2, or the data that is being read from the disk 3 into the available area 2A. The CPU therefore need not perform a read operation of data from the disk 3, but gives the HDC 1 an instruction to start data transfer.
Upon reception of this instruction from the CPU, the HDC 1 starts transferring the data stored in the area 2B of the buffer memory 2 to the host system 200, or starts data transfer thereto when a predetermined amount of data is stored in the area 2A (step S35). When a read command as a sequential access request is issued again from the host system 200 afterward, the above operation is repeated (steps S31, S35, and S36).
Assume that a read command as a repeat access request is issued from the host system 200 (YES in step S32). That is, this command is an access request for requested data having the same address as that of requested data corresponding to the immediately preceding read command.
At this time, the requested data has been read from the disk 3 and stored in the area 2A of the buffer memory 2 upon processing associated with the immediately preceding read command. As described above, however, when the requested data in the area 2A of the buffer memory 2 is completely transferred to the host system 200 by the processing associated with the immediately preceding read command, the area 2A is recognized as an available area. For this reason, there is a possibility that data consecutive to the data stored in the area 2B has been read from the disk 3 and stored in the area 2A (i.e., an overwrite operation). That is, there is a possibility that the requested data corresponding to the repeat access request has been erased from the buffer memory 2.
Upon reception of a read command as a repeat access request, the CPU therefore gives the HDC 1 an instruction to immediately stop a read operation of data from the disk 3 (YES in step S32; step S37). After this processing, the HDC 1 transfers the requested data stored in the area 2A of the buffer memory 2 to the host system 200 (YES in step S38; step S35). If no request data is left in the area 2A of the buffer memory 2 in spite of the operation of stopping the data read operation, the CPU gives the HDC 1 an instruction to read data from the disk 3 (NO in step S38). In according to this instruction, the HDC 1 reads the requested data from the disk 3 and stores it in the buffer memory 2, and further reads successive data and stores it in the buffer memory 2 as long as the buffer memory 2 has an available area (step S34).
In such a conventional cache system, upon reception of a repeat access request from the host system, the CPU stops a read operation of data from the disk to minimize the possibility that the requested data stored in the buffer memory is overwritten and erased by successive data. This processing poses the following inconvenience.
The processing of reading data following requested data from the disk and storing it in the buffer memory allows cache processing to effectively function with respect to a sequential access request from the host system. If, therefore, a read operation of successive data from the disk is stopped, when a sequential access request is generated, no requested data is stored in the buffer memory. That is, a miss hit occurs. As a result, the HDC reads the requested data from the disk again and stores it in the buffer memory. The processing time required to transfer the requested data to the host system become inevitably longer than that when the requested data is stored in the buffer memory, i.e., a hit occurs.
As described above, when a repeat access request is generated, the disk access processing is immediately stopped. For this reason, the amount of consecutive data (successive data) read from the disk into the buffer memory varies in accordance with the intervals at which read commands as access requests are issued from the host system. More specifically, as the intervals at which command are issued from the host system shorten, the amount of successive data stored in the buffer memory decreases, and vice versa.
For this reason, as the command issuing intervals in the host system shortens, i.e., the processing speed in the host system increases, the amount of successive data stored in the buffer memory decreases. The hit rate with respect to sequential access requests from the host system, in particular, therefore decreases. As a result, the data access efficiency decreases.